Anjan Govindaraju
SoC Physical Design/ Project Management
Summary
- 8 years of experience as a Physical design engineer working on as low as 5nm nodes taking the design through Synthesis, PNR flow, analysis in PrimeTime and automation in TCL and PERL.
- Well versed in CAD tools such as ICC, ICC2, Encounter, Innovus, DC topo and Primetime.
- 2 years of agile project management experience steering the team through RTL Design, Verification and Implementation tasks on 5nm SoC using JIRA software.
Overview
16
16
years of professional experience
1
1
Certification
Work History
Physical Design Engineer/ SoC Project Management
Nokia
02.2020 - Current
- Delivered multiple 5nm node DC-topo synthesized netlists with timing closure and power /area constraints within targets to the vendor.
- Set up Synthesis, Formality & Primepower flows & automation in TCL
- Led cross-functional teams to successfully carry out system-on-chip (SoC) projects in RTL design, Implementation and Verification, ensuring adherence to project timelines and budgets
- Provided guidance to junior team members on physical design techniques and methodologies
- Conducted regular design, implementation and verification reviews to steer project seamlessly and complete timely deliverables using agile methodologies such as JIRA.
Sr.Physical Design Engineer
Intel
11.2018 - 10.2019
- Hands-on experience with design debug and closure of a 10nm ASIC
server chip including synthesis and PNR. - Managed a team for automation of PNR scripts.
Sr. Physical Design Engineer
Insilico
10.2017 - 11.2018
- Developed PERL scripts to purge data of a post placement optimization timing run across various modes.
- Automated power and signal routing of RDL layers in a 14nm design & DRC fixes (shorts, Opens, Min spacing) and customized PLL routing automation using TCL scripts.
Sr. Physical Design Engineer
Cerium Systems
01.2017 - 09.2017
- Fixed DRC and LVS issues manually in ICC on a congested design (shorts, opens, antenna issues, via enclosure, off-grid, illegal tracks and non-preferred routing layers were all fixed)
- Delivered TCL scripts to automate all the vias for RDL routing
Sr. Physical Design Engineer
Sankalp Semiconductor
03.2015 - 12.2016
- Set up the INNOVUS flow and closed the design in PNR and DRC / LVS for a 130nm design
- Analyzed and fixed timing issues in PT and provided ECOs to the PnR team
- Manual timing fixes in mmmc corners using upsizing, relocation and buffering techniques.
- Complete RTL level netlist to gate level netlist (Synthesis) flow using RTL Compiler to ensure projects are delivered in time.
Analog and Mixed signal Product development and Test Engineer
Qualcomm Inc
01.2012 - 02.2015
- Developed WLAN and GPS baseband receivers' spectral analysis tests focusing on device verification, performance optimization and characterization using Labview on multiple 28nm and 20nm projects.
Physical Design Engineer
MindTree Limited
10.2007 - 07.2009
- Implemented placement and routing of a PLL block in a digital die resolving any signal integrity issues.
- PNR of a digital block in 180nm.
Education
Master of Science - Electrical Engineering
University of Texas At Arlington
Texas, USA 05.2009 - 2012.05
Bachelor of Science - Electronics and Telecommunications
PES Institute of Technology
Bangalore, India 05.2003 - 2007.05
Skills
TCL and PERL scripting
Certification
PRINCE2 Foundation and Practitioner
Timeline
Physical Design Engineer/ SoC Project Management
Nokia
02.2020 - Current
Sr.Physical Design Engineer
Intel
11.2018 - 10.2019
Sr. Physical Design Engineer
Insilico
10.2017 - 11.2018
Sr. Physical Design Engineer
Cerium Systems
01.2017 - 09.2017
Sr. Physical Design Engineer
Sankalp Semiconductor
03.2015 - 12.2016
Analog and Mixed signal Product development and Test Engineer
Qualcomm Inc
01.2012 - 02.2015
Master of Science - Electrical Engineering
University of Texas At Arlington
05.2009 - 2012.05
Physical Design Engineer
MindTree Limited
10.2007 - 07.2009
Bachelor of Science - Electronics and Telecommunications
PES Institute of Technology
05.2003 - 2007.05
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